Moore's law is perhaps one of the best known trends among a wide range of technologies relating to semiconductor integrated circuits. Moore's law describes a trend in computing hardware where the number of transistors that can be placed inexpensively on an integrated circuit doubles approximately every two years. This trend has continued for more than half a century and is expected to continue for at least the next few years. Moore's law has served the industry well and has even been incorporated for decades into the International Technology Roadmap for Semiconductors, known throughout the world as ITRS, for guiding long-term planning and setting targets for research and development.
The cost of making smaller and smaller critical dimensions (nodes) on semiconductor integrated circuits has been increasing dramatically the past few years during the transition from i-Line to KrF to ArF and now to the newly emerging extreme ultraviolet (EUV) photolithography technologies. In view of this, a few industry experts have contended that there is not much farther the semiconductor industry can cost effectively reduce the size of critical dimensions on semiconductor integrated circuits in the same time frame as stated by Moore's Law.
However, there is another mechanism that can be used to improve performance which relates to the packaging of the integrated circuits. Once a wafer of integrated circuits is completed and diced, the integrated circuit needs to be packaged to be of use. FIG. 1 (PRIOR ART) is a diagram illustrating how the packaging of integrated circuits has evolved over the years from wire bound 102, flip chip 104, stacked die 106, package-on-package 108 to the emerging three-dimensional integrated circuit 110 (3D IC 110). The semiconductor industry has undertaken an increasingly aggressive approach to develop, adapt, and implement the emerging 3D IC packaging technology.
The three-dimensional integrated circuit 110 (3D IC 110) is a semiconductor circuit in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. 3D IC packaging should not be confused with 3D packaging which has been in use for years and saves space by stacking separate chips in a single package. The 3D packaging also known as System in Package (SiP) does not integrate the chips into a single circuit. In particular, the chips in the SiP communicate with off-chip controls much as if they were mounted in separate packages on a normal circuit board.
In contrast, the 3D IC 110 acts as a single chip where all the components on the different layers communicate with on-chip controls either vertically or horizontally. Basically, the new 3D IC packaging technology by stacking integrated circuits, or die, on top of each other results in a 3D IC 110 which has improved speed, reduced power, and reduced cost when compared to the ICs manufactured by the other packaging technologies. In fact, the advantages associated with 3D IC packaging could help extend the performance of Moore's law and possibly extend the performance even more than predicted by Moore's law.
The 3D IC packaging technology can be used to fabricate many different types of three-dimensional integrated circuits from, for example, memory stacks to Field Programmable Gate Arrays (FPGAs). Referring to FIG. 2 (PRIOR ART), there is a photo of a Xilinx 3D IC FPGA 200 incorporating a silicon interposer 202 that is manufactured by Taiwan Semiconductor Manufacturing Company. The Xilinx 3D IC FPGA 200 comprises a FPGA slice 204 which includes redistribution layers 205 with micro bumps 206 formed thereon where the FPGA slice 204 is positioned next to one side of the silicon interposer 202. The other side of the silicon interposer 202 is positioned next to a wiring board 208208 which has redistribution layers 207 with C4 bumps 210 located thereon. The silicon interposer 202 has vias 212 (known as through silicon vias (TSVs) 212) which are filled with copper 214 to provide precision interconnects between the micro bumps 206 and the C4 bumps 210. The wiring board 208 has redistribution layers 209 on another side thereof which are used to connect the C4 bumps 210 to ball grid arrays 211 (BGAs 211) which are attached to a motherboard 215. The architecture of the Xilinx 3D IC FPGA 200 is commonly referred to as a “2.5D IC” because there are multiple ICs on the interposer as opposed to a vertical stack of multiple ICs.
In this particular example, the silicon interposer 202 provides the precision interconnects (vias 212 filled with copper 214) for the FPGA slice 204 and the wiring board 208 while also functioning to provide electrical separation (electrical isolation) between the FPGA slice 204 and the BGA 208. Typically, the silicon interposer 202 has vias 212 (TSVs 212) that are formed with relatively good quality using the Dry Reactive Ion Etch process (DRIE) which is also known in the industry as the “Bosch process”. However, the DRIE process is not perfect. For example, the DRIE process cost significantly more when compared to the more conventional wire bond process, where the die connections are made along the periphery of the die directly to the packaging substrate. The wire bond process is not used to make a 3D IC 110 but nevertheless helps to illustrate the significant costs associated with the DRIE process.
Referring to FIG. 3 (PRIOR ART) there is a graph which illustrates the different steps and associated relative costs for performing the wire bond process 300 and the DRIE process 302 utilizing a 300 mm outer diameter silicon wafer. The DRIE process 302 in this example shows the steps and associated costs of forming vias 212 (TSVs 212) in the 300 mm outer diameter silicon wafer at 10 μm/min 302a, 20 μm/min 302b, 30 μm/min 302c, 40 μm/min 302d, and 50 μm/min 302e. The different steps in the wire bond process 300 and the DRIE process 302 are represented according to the following legend:                lithography step 304        etching step 306        strip/clean step 308        dielectric liner step 310        barrier and seed steps 312        lithography step 314        Cu electroplating and solder steps 316        strip step 318        wet etch barrier and seed steps 320        back grind and polish steps 322        die attach film step 324        via exposure step and via dielectric opening step 326        dicing (saw) step 328        pick & place and die attach steps 330        wire bond step 332        
As the graph in FIG. 3 illustrates, the silicon interposers 202 with copper-filled vias 212 and 214 made by the DRIE process have a relatively high manufacturing cost. Accordingly, there is a need to address this shortcoming and other shortcomings associated with the traditional silicon interposer. This need and other needs are satisfied by the present invention.